The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structure and fabrication methods of MOS transistors, which have an additional implant under the channel compared to standard technology.
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (xe2x80x9cHuman Body Modelxe2x80x9d, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (xe2x80x9cmachine modelxe2x80x9d, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the xe2x80x9ccharged device modelxe2x80x9d (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, xe2x80x9cESD in Silicon Integrated Circuitsxe2x80x9d (John Wiley and Sons LTD. London 1995), and C. Duvvury, xe2x80x9cESD: Design for IC Chip Quality and Reliabilityxe2x80x9d (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fieldsxe2x80x94all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an NMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the NMOS device width from the drain to the source under the gate oxide of the NMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that NMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the NMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak NMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Such substrate biasing can be effective at improving the response of a multi-finger MOS transistor that is used to conduct an ESD discharge to ground. However, substrate biasing can cause the threshold voltages for devices to change from their nominal values, which may affect device operation. In addition, substrate biasing under steady-state conditions causes heat generation and increases power losses.
Solutions offered in known technology require additional IC elements, silicon real estate, and/or process steps (especially photomask alignment steps). Their fabrication is, therefore, expensive. Examples of device structures and methods are described in U.S. Pat. No. 5,539,233, issued Jul. 23, 1996 (Amerasekera et al., xe2x80x9cControlled Low Collector Breakdown Voltage Vertical Transistor for ESD Protection Circuitsxe2x80x9d); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekera et al., xe2x80x9cMethod for Designing Shallow Junction, Salicided NMOS Transistors with Decreased Electrostatic Discharge Sensitivityxe2x80x9d); U.S. Pat. No. 5,940,258, issued Aug. 17, 1999 (Duvvury, xe2x80x9cSemiconductor ESD Protection Circuitxe2x80x9d); U.S. Pat. No. 6,137,144, issued Oct. 24, 2000, and U.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, xe2x80x9cOn-Chip ESD Protection in Dual Voltage CMOS); and U.S. patent application Ser. No. 09/456,036, filed Dec. 3, 1999 (Amerasekera et al., xe2x80x9cElectrostatic Discharge Device and Methodxe2x80x9d).
The influence of substrate well profiles on the device ESD performance is investigated, for instance, in xe2x80x9cInfluence of Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 xcexcm CMOS Technologyxe2x80x9d (K. Bock, C. Russ, G. Badenes, G. Groeseneken and L. Deferm, Proc. EOS/ESD Symp., 1997, pp. 308-315). However, known technology recommends only a lower epitaxial doping or a lower implant dose as methods to increase the p-well resistance.
The challenge of cost reduction implies a drive for minimizing the number of process steps, especially a minimum number of photomask steps, and the application of standardized process conditions wherever possible. These constraints should be kept in mind when additional process steps or new process conditions are proposed to improve ESD insensitivity without sacrificing any desirable device characteristics. An urgent need has, therefore, arisen for a coherent, low-cost method of enhancing ESD insensitivity without the need for additional, real-estate consuming protection devices. The device structure should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
A lateral NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a stopping region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate. The transistor further has in its p-well a region of higher resistivity than the remainder of the well; this region extends laterally from one recessed region to the other, and vertically from a depth just below the depletion regions to the depth of the stopping region.
According to the invention, this region of higher p-type resistivity is created by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants adjusting the threshold voltage and creating the p-well and channel stop.
In an ESD event, this region of higher resistivity increases the current gain of the parasitic lateral npn bipolar transistor and thus raises the current It2, which initiates the thermal breakdown with its destructive localized heating.
When the gate, source and substrate terminals are at 0 V and the drain at positive potential, the current gain xcex2 of the lateral bipolar npn transistor in the ESD event is defined as
xcex2=(Idxe2x88x92Igen)/(Igenxe2x88x92Isub),
where
Id=drain current,
Igen=Ib+Isub,
Ib=base current,
Isub=hole current from the collector junction through the substrate to the backside contact.
It is an aspect of the invention that the region of higher resistivity is the substrate of the transistor, enabling full functioning. of the transistor while not affecting operation of neighboring active devices.
Another aspect of the invention is that the region of higher resistivity improves the ESD protection of the transistor without decreasing latch-up robustness or increasing inadvertent substrate current-induced body biasing of neighboring transistors.
Another aspect of the invention is that it is equally applicable to PMOS transistors; the conductivity types of the semiconductor and the ion implant types are simply reversed.
The method of fabricating the region of higher resistivity under the active area of a high-voltage NMOS transistor having a gate comprises the steps of depositing a photoresist layer over the transistor and opening a window in this layer over the active area of the transistor; then implanting, at high energy, n-doping ions into the p-type semiconductor substrate through the window, creating a deep region having a net p-type doping lower than that of the p-type semiconductor remote from the transistor active area. A preferred depth of the region is between 50 and 150 nm. A region too deep would require higher implant energy with possibly more damage and thus higher junction leakage current or junction isolation failure.
It is an essential aspect of the present invention that this high-energy ion implant is performed without the need for a new photomask step. This economical feature renders the additional high-energy ion implant step of the present invention exceedingly inexpensive.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.